1. Field of the Invention
The present invention relates to strained-channel PMOS transistors and, more particularly, to a method of substantially reducing the formation of SiGe abnormal growths on polycrystalline electrodes for strained-channel PMOS transistors.
2. Description of the Related Art
A MOS transistor is a well-known semiconductor device that includes spaced-apart source and drain regions, which are separated by a channel, and a gate that lies over and insulated from the channel. MOS transistors can be formed as n-channel (NMOS) devices or as p-channel (PMOS) devices.
FIG. 1 shows a cross-sectional view that illustrates a prior-art PMOS transistor 100. As shown in FIG. 1, PMOS transistor 100 includes a semiconductor body 110. Semiconductor body 110, in turn, includes an n-type single-crystal-silicon substrate region 112, and spaced-apart p-type single-crystal-silicon source and drain regions 114 and 116 that touch substrate region 112. Source region 114 and drain region 116 each include a heavily-doped (p+) region and a lightly-doped (p−) region.
Semiconductor body 110 further includes a channel portion 120 of substrate region 112 that lies between and touches the p-type source and drain regions 114 and 116. In addition, semiconductor body 110 includes a shallow trench isolation (STI) region 122 that touches substrate region 112 and the p-type source and drain regions 114 and 116.
As further shown in FIG. 1, PMOS transistor 100 also includes a gate insulation region 130 that lies over channel portion 120, and a polycrystalline silicon (poly-Si) gate 132 that lies on gate insulation region 130 over channel portion 120. Further, transistor 100 includes a non-conductive side wall spacer 134 that laterally surrounds poly gate 132.
In operation, when a negative drain-to-source voltage VDS is present, and the gate-to-source voltage VGS is more negative than the threshold voltage, PMOS transistor 100 turns on and holes flow from source region 114 to drain region 116. When the gate-to-source voltage VGS is more positive than the threshold voltage, PMOS transistor 100 turns off and no holes (other than a very small leakage current) flow from source region 114 to drain region 116.
To enhance the mobility of the holes that flow from the source region to the drain region, advanced devices utilize a strained-channel PMOS transistor in lieu of a conventional PMOS transistor, such as PMOS transistor 100. Strained-channel PMOS transistors, in turn, utilize silicon germanium (SiGe) source and drain regions in lieu of the single-crystal-silicon source and drain regions utilized by conventional PMOS transistors.
FIG. 2 shows a cross-sectional view that illustrates a prior-art strained-channel PMOS transistor 200. PMOS transistor 200 is similar to PMOS transistor 100 and, as a result, utilizes the same reference numerals to designate the elements which are common to both of the PMOS transistors.
As shown in FIG. 2, one significant way that PMOS transistor 200 differs from PMOS transistor 100 is that PMOS transistor 200 replaces substantial portions of the p-type single-crystal-silicon source and drain regions 114 and 116 with p-type SiGe source and drain regions 210 and 212. The SiGe source and drain regions 210 and 212 introduce strain into channel portion 120, which increases the hole mobility when PMOS transistor 200 is turned on.
One problem with strained-channel PMOS transistor 200 is that the conventional approach to forming PMOS transistor 200 is susceptible to the formation of SiGe abnormal growths on the poly-Si gate electrodes. The SiGe abnormal growths, which can be undesirably formed when the SiGe source and drain regions 210 and 212 are epitaxially grown, degrade device yield.
FIGS. 3A-3L show a series of cross-sectional views that illustrate a prior-art method 300 of forming a strained-channel PMOS transistor. As shown in FIG. 3A, method 300 utilizes a semiconductor body 310 which has been conventionally formed to have an n-type single-crystal-silicon substrate region 312, a gate isolation region 314 that touches substrate region 312, and a shallow trench isolation region (STI) 316 that touches and extends into substrate region 312, and laterally surrounds gate isolation region 314. Gate isolation region 314 can be implemented with, for example, silicon dioxide (SiO2) or silicon oxynitride (SiON).
As further shown in FIG. 3A, method 300 begins by forming a polycrystalline (poly) layer 320 on gate isolation region 314 and STI region 316 in a conventional manner. Poly layer 320 can be implemented with, for example, undoped polycrystalline silicon or undoped polycrystalline silicon germanium. After poly layer 320 has been formed, an inorganic anti-reflective coating (IARC) layer 324 is conventionally formed on poly layer 320. Next, a patterned photoresist layer 326 is formed on the top surface of IARC layer 324 in a conventional fashion.
As shown in FIG. 3B, after patterned photoresist layer 326 has been formed, the exposed region of IARC layer 324 is conventionally etched to form an IARC hard mask 330. After IARC hard mask 330 has been formed, patterned photoresist layer 326 is removed in a conventional manner using, for example, oxygen or fluorine ashing. Following this, the resulting structure is cleaned to remove organics, such as with a wet etch (e.g., a Piranha etch) or a dry etch.
As shown in FIG. 3C, following the removal of patterned photoresist layer 326, the exposed regions of poly layer 320 and gate isolation region 314 are anisotropically etched in a conventional fashion. The etch forms a stacked structure 331 that touches substrate region 312. Stacked structure 331 includes IARC hard mask 330, a poly gate electrode 334 which touches and lies below IARC hard mask 330, and a gate insulation region 336 that touches and lies between gate electrode 334 and substrate region 312. As a result of gate insulation region 336, poly gate electrode 334 is electrically isolated from substrate region 312.
After this, as shown in FIG. 3D, a non-conductive layer 340 is formed to touch substrate region 312, STI region 316, IARC hard mask 330, gate electrode 334, and gate insulation region 336. Non-conductive layer 340 can be implemented with, for example, an oxide layer or an oxide-nitride-oxide (ONO) layer.
As shown in FIG. 3E, once non-conductive layer 340 has been formed, non-conductive layer 340 is anisotropically etched in a conventional manner. Following the anisotropic etch, the remaining portion of non-conductive layer 340 is isotropically etched with an etchant, such as dilute hydrofluoric acid (dHF), to form a non-conductive side wall spacer 342 that touches the side wall of poly gate electrode 334. In some cases, as shown by the arrow A in FIG. 3E, the dHF etch can remove a top portion of side wall spacer 342 and expose a significant portion of the side wall of IARC hard mask 330.
As shown in FIG. 3F, after side wall spacer 342 has been formed, a p-type dopant is implanted into substrate region 312 and driven in using conventional procedures to form single-crystal-silicon PLDD source and drain regions 344 and 345. Next, a protection layer 346 is formed to touch STI region 316, IARC hard mask 330, side wall spacer 342, and the PLDD regions 344 and 345.
Protection layer 346 can be implemented with, for example, a nitride layer, and formed in a conventional low-temperature manner using, for example, hexachlorodisilane (HCD) or tertiary-butylamino silane (BTBAS) processes. Once protection layer 346 has been formed, a patterned photoresist layer 348 is formed on protection layer 346. (Patterned photoresist layer 348 protects other areas of the wafer from the subsequent etch of protection layer 346.)
Following this, as shown in FIG. 3G, protection layer 346 is anisotropically etched in a conventional manner to form a non-conductive side wall spacer 350. In addition, the etch exposes spaced-apart regions of the single-crystal-silicon PLDD regions 344 and 345. In some cases, as shown by the arrow B in FIG. 3G, variations in the manufacturing process, such as the non-uniform deposition of protection layer 346, can cause the etch to undesirably re-expose a significant portion of the side wall of IARC hard mask 330.
As shown in FIG. 3H, after side wall spacer 350 has been formed, the exposed portions of the single-crystal-silicon PLDD regions 344 and single-crystal-silicon substrate region 312 are anisotropically etched to form source and drain trenches 352 and 354. Once the source and drain trenches 352 and 354 have been formed, patterned photoresist layer 348 is removed.
Next, as shown in FIG. 3I, the exposed portions of single-crystal-silicon in the source and drain trenches 352 and 354 are wet etched to form source and drain cavities 356 and 358. As further shown in FIG. 3I, a channel portion 359 of the single-crystal-silicon substrate region 312 lies horizontally between the source and drain cavities 356 and 358. Channel portion 359, in turn, lies directly below poly gate electrode 334.
Following this, as shown in FIG. 3J, p-type silicon germanium is epitaxially grown in a conventional manner to form p-type SiGe source and drain regions 360 and 362 in the source and drain cavities 356 and 358. Next, as shown in FIG. 3K, IARC hard mask 330, protection layer 346, and side wall spacer 350 are removed in a conventional manner to form a strained-channel PMOS transistor 370.
One of the problems with the conventional formation of strained-channel PMOS transistors, such as PMOS transistor 370, is that, due in part to the undesirable exposure of the side wall region of IARC hard mask 330, IARC hard mask 330 can partially chip or lift off from gate electrode 334, thereby exposing a portion of gate electrode 334.
When this occurs, as shown in FIG. 3L, a SiGe abnormal growth 372 is undesirably formed on the exposed region of gate electrode 334 at the same time that the SiGe source and drain regions 360 and 362 are formed. SiGe abnormal growths 372 can lead to the formation of defective transistors. As a result, there is a need for a method of substantially reducing the formation of SiGe abnormal growths.